Aspect enhanced functional coverage driven verification in the SystemC HDVL

Abstract

As embedded systems incorporate more and more amounts of IP and embedded software the functional and nonfunctional verification task is one of the key bottlenecks in the design process. Despite proprietary design and verification languages such as IEEE-1800 SystemVerilog and IEEE-1647 e offer CDV functionalities neither SystemC or the SCV addon library contain these features. Moreover, as programming languages and verification paradigms of the hardware and software domain continue to converge the verification techniques and methodologies need to take account of that, e.g. by adaption of the aspect-oriented programming scheme. In this paper we describe an approach for enhancing the functional coverage collection in the SystemC ecosystem by means of aspects, allowing cross-cutting the concern of CDV verification in stand-alone aspects, increasing the overall verification productivity.