ESD protection design for mixed-power domains in 90nm CMOS with new efficient power clamp and GND current trigger (GCT) technique

Abstract

This paper presents an ESD protection design scheme for mixed-power domains in narrow ESD design window with ultra-thin gate oxides. Using a grounded gate (gg)NMOS-based clamp with contact ballast (CTB) layout technique, a factor of 3X area reduction can be achieved for MM protection of a 1.6 nm gate oxide compared to a conventional silicide-block ESD scheme. To expand the design window, a novel ground current trigger (GCT) technique using current sensing circuit between different GND busses is proposed. 7 kV HBM and 550 V MM can be achieved with a 2nd clamp with GCT technique, with the same area as a conventional snapback protection device. The GCT technique is also effective for SCR trigger element as cross clamp.