A 4-Mbit Non-Volatile Chalcogenide Random Access Memory

Abstract

During the first stage of a multi-year research program, BAE SYSTEMS and Ovonyx have designed, fabricated and tested a series of test chips to demonstrate full integration of a chalcogenide-based non-volatile memory element into a radiation hardened CMOS process. The test structures range from simple two- and four-point-probe material characterization macros, such as sheet resistance monitors and chalcogenide memory elements, to fully wired 64kbit memory arrays. Process integration has progressed from the previously demonstrated stand-alone chalcogenide memory elements through full memory array fabrication. Results of successful integration of the chalcogenide material used for phase-change applications in re-writable optical storage (Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Sb <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Te <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sub> ) with BAE SYSTEMS' 0.5mum radiation hardened CMOS to produce 64kbit arrays have been reported in the past. In this paper we present a description of the architecture and design of a 4Mbit, chalcogenide non-volatile memory for a 0.25mum radiation hardened CMOS process. Fabrication of the design was completed in early 2005. Electrical test results of the 4Mb chalcogenide memory hardware are presented at the conference. In addition, results from the C-RAM process transition (from BAE SYSTEMS' 0.5mum to the radiation hardened 0.25mum process) are presented