Temperature-aware routing in 3D ICs

TLDR

3D integrated circuits improve performance but generate significant heat per unit volume, requiring electrothermally‑conscious design. The paper proposes a temperature‑aware 3D global routing algorithm that inserts thermal vias and wires to lower effective thermal resistance and reduce chip temperature. The algorithm uses sensitivity analysis to judiciously allocate thermal vias and wires, iteratively resolving contention between routing and thermal structures. Experiments demonstrate that the algorithm reduces peak temperature and alleviates routing congestion.

Abstract

3D integrated circuits (3D ICs) provide an attractive solution for improving circuit performance. Such solutions must be embedded in an electrothermally-conscious design methodology, since 3D ICs generate a significant amount of heat per unit volume. In this paper, we propose a temperature-aware 3D global routing algorithm with insertion of and to lower the effective thermal resistance of the material, thereby reducing chip temperature. Since thermal vias and thermal wires take up lateral routing space, our algorithm utilizes sensitivity analysis to judiciously allocate their usage, and iteratively resolve contention between routing and thermal vias and thermal wires. Experimental results show that our routing algorithm can effectively reduce the peak temperature and alleviate routing congestion.