A formal specification language for PLC-based control logic

Abstract

Formal verification, using model checking tools, is promising in developing (IEC 61131) industrial control logic. Formal verification requires a formal specification of the properties to be verified. Specifications in model checking tools are typically expressed using temporal logic. However, the standard temporal logic dialects are not well suited for control engineers who do rarely have a background within computer science. In this paper a new dialect of linear temporal logic, ST-LTL, is introduced that intends to be easier to use for control engineers than the existing dialects. The relation of ST-LTL compared to existing temporal logic dialects is analyzed.