System Design Framework and Methodology for Xilinx Virtex FPGA Configuration Scrubbers

Abstract

SRAM-based FPGAs, like Xilinx Virtex series, are susceptible to ionizing radiation and require configuration memory scrubbing in order to be used in harsh radiation environments. The scrubbing is typically performed by a scrubber device external to the FPGA (via configuration ports). A design framework and methodology for such scrubbers is described in this paper. The framework is based on SystemC modeling language and includes a Scrubber Model, a Supervisor Model, an FPGA Model and a Fault Injector Model. The framework allows simulating scrubbing algorithms and the configuration links at frame level or physical levels (SelectMAP or JTAG). The designer can define scrub and fault injection rates, frame and fault lists, fault detection methods, etc. With the proposed framework and methodology, the designer can explore the scrubber design space in advance to any hardware implementation.