A mostly digital variable-rate continuous-time ADC ΔΣ modulator

Abstract

A mostly digital variable-rate continuous-time ΔΣ modulator is presented with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8 to 17 mW, 0.5 to 1.15 GHz, 3.9 to 18 MHz, and 67 to 78 dB, respectively. The IC is implemented in a 65 nm CMOS process with an active area of 0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .