A CMOS programmable gain amplifier with a novel DC-offset cancellation technique

Abstract

A programmable gain amplifier (PGA) with a novel DC offset cancellation (DCOC) technique for IEEE 802.11b/g wireless LAN direct-conversion receiver (DCR) is presented. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this PGA design. A gain tuning range of 0 dB to 56 dB with 2 dB per step is achieved. The DCOC loop is based on a voltage-current negative feedback that includes a switchable bandwidth algorithm to speed up the settling time of DCOC. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated in a 0.13 μm CMOS technology, this PGA dissipates 9.7 mW from a 1.2 V supply voltage and occupies an area of 0.17 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .