Error Correcting Cyclic Redundancy Checks based on Confidence Declaration

Abstract

Cyclic redundancy check is one of the most popular methods of error detection for digital signals, whereas it has not the inherent capability of correcting multi-bit errors and most of the existing works focus on algorithm optimization of CRC. Take example for the Mode S downlink error correction, this paper investigates two multi-bit error correction techniques using cyclic redundancy checks based on bit and confidence declaration and presents a combined process flow for correcting both burst and random errors. Both techniques enhance the error correction capability of cyclic redundancy check while not adding more redundancy