Dielectric scaling of a top gate silicon nanowire on insulator transistor

Abstract

The effects of gate dielectric constant and thickness on the performance of a top gate silicon nanowire on insulator transistor are studied using three-dimensional quantum simulation. The replacement of SiO2 by a high-K dielectric improves the off-state current, the on/off-current ratio, the inverse subthreshold slope, and the channel transconductance and degrades the switching performance. The high-K gate dielectric provides better control of the channel potential, especially in the off-state, and improves the off-state tunneling current by almost two orders of magnitude. With high-K dielectric, the switching performance degrades primarily due to increase in gate capacitance. The gate has better control of channel potential with thinner oxide. The on/off-current ratio, inverse subthreshold slope, channel transconductance, and the switching performance improve with thinner gate oxide. Our device of 10 nm gate length, 1 nm oxide with dielectric constant of 10, has an on/off-current ratio of 1.16×108, an inverse subthreshold slope of 70.5 mV/decade, and the intrinsic unity current gain frequency of 2.7414 THz.