Power-Delay Metrics Revisited for 90nm CMOS Technology

Abstract

Recently, designers have been using the energy-delay product as a metric of goodness for CMOS designs due to certain perceived shortcomings of the more traditional power-delay product. As the industry moves to 90 nm technology, with higher leakage currents, it is an appropriate time to revisit existing design metrics. We provide a more general view of power and delay metrics for design optimization and then illustrate how these metrics can be used. To do so, a re-evaluation of the metrics, based on past and future trends, is carried out and a set of new metrics is proposed. Interestingly, the dominance of leakage power at 90 nm technology and beyond tends to reduce the feasible operating region. We also establish a fundamental relationship between the optimal operating points and the generalized design metrics. Moreover, our initial findings indicate that some designs may need to leak more than expected to achieve certain design targets, running somewhat counter to conventional wisdom.