A 40-to-800MHz Locking Multi-Phase DLL

Abstract

A delay matrix and a gradual switching of shunt capacitors in delay cells are proposed for a wide-range-locking multi-phase DLL. With an interpolating resistor network, delay step error is greatly reduced by error averaging. The DLL, implemented in 0.13mum CMOS, has a locking range of 40 to 800MHz. With 40 phases, the maximum delay step error is 16.7ps at 700MHz. The chip dissipates 43mW at 700MHz from a 1.2V supply and the measured jitter is 12ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> and 1.6ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> .