A 0.9 V 0.4–6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration

Abstract

A software-defined radio receiver is presented, operating from 400 MHz to 6 GHz. The split front-end architecture has a low-band RF path (0.4-3 GHz) using 8-phase passive mixers and a high-band RF path (3-6 GHz) using 4-phase passive mixers. DC-offset, IIP 2, and harmonic recombination for harmonic rejection may be calibrated to achieve true wideband specifications. A 0.5-50 MHz tunable baseband bandwidth implies compliance with LTE and future standards. Despite having a 0.9 V supply, the receiver architecture ensures high out-of-band linearity. The 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , 28 nm CMOS receiver achieves down to 1.8 dB NF, >+3 dBm out-of-band IIP3, >70 dB calibrated HR3/5 and >+80 dBm calibrated IIP2. It tolerates 0 dBm blockers at 80 MHz offset with a blocker NF of 10 dB for a power consumption of 20-40 mW.