EURASIP Journal on Advances in Signal Processing · 2008 · 44 citations · 22 references
EngineeringComputer EngineeringElectrical EngineeringField-programmable Gate ArraysReconfigurable ComputingWireless CommunicationsChannel EstimationDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationLow-power Fpga DesignDigital Signal Processing Block ArchitectureDigital Signal Processing BlocksField-programmable Gate Array-based Embedded SystemsMimoMimo SystemsMultiple-input Multiple-output CommunicationReconfigurable Hardware Architecture
Design and implementation of a highly optimized MIMO (multiple-input multiple-output) detector requires cooptimization of the algorithm with the underlying hardware architecture. Special attention must be paid to application requirements such as throughput, latency, and resource constraints. In this work, we focus on a highly optimized matrix inversion free MMSE (minimum mean square error) MIMO detector implementation. The work has resulted in a real-time field-programmable gate array-based implementation (FPGA-) on a Xilinx Virtex-2 6000 using only 9003 logic slices, 66 multipliers, and 24 Block RAMs (less than 33% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput with a small 2.77-microsecond latency. The designed linear MMSE MIMO detector is capable of complying with the proposed IEEE 802.11n standard.
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Capacity of Multi‐antenna Gaussian Channels
Emre Telatar · European Transactions on Telecommunications · 1999 · 11.3K citations · Full text
An Overview of MIMO Communications—A Key to Gigabit Wireless
A. Paulraj, D. Gore, R.U. Nabar et al. · Proceedings of the IEEE · 2004 · 2.1K citations