Design for testability in digitally-corrected ADCs

Abstract

A test methodology that reveals safety-margin problems is presented. The methodology allows diagnosis without additional hardware. To test the safety margin, the correction logic is inhibited. The coding of the first and second stages actually remains the same, but the first stage output is never decremented before the two stage outputs are combined to form the overall ADC (analog-to-digital converter) output code. This means that over a portion of the second-stage range, the ADC output code will be too high. An example of how a first-stage flash error is interpreted is shown. Here the safety margin is reduced by the shift of the first-stage transition. The technique described here has been demonstrated on a CMOS 10-b, 20-Ms/s ADC for camcorder applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>