A 78mW 11.8Gb/s serial link transceiver with adaptive RX equalization and baud-rate CDR in 32nm CMOS

Abstract

An 11.8 Gb/s transceiver with 3-tap FIR TX and adaptively equalized RXis implemented in a 32 nm CMOS process. The RX features a continuous-time LE with AGC, a 4-tap DFE and baud-rate timing recovery. The transceiver achieves a BER<2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> with PRBS23 over a 24" PCB trace with 25 dB loss at 5.9 GHz. The TX/RX lane occupies 0.155 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 78 mW from a 0.95 V supply when operating at 11.8 Gb/s.