IEEE Transactions on Industrial Electronics · 2014 · 87 citations · 24 references
Torn CircuitEngineeringVlsi DesignPower Electronics ConverterComputer ArchitecturePower ElectronicsNetwork Tearing TechniqueModeling And SimulationFpga-based Real-time SimulationParallel ComputingCircuit AnalysisElectrical EngineeringComputer EngineeringTime StepsPower System ProtectionReal-time SimulationMicroelectronicsCircuit DesignPower ConvertersField-programmable Gate ArraysCircuit Simulation
Hardware‑in‑the‑loop simulation uses FPGAs to achieve sub‑microsecond time steps, which are critical for aerospace and automotive power converters operating at 10–200 kHz. This work introduces a network‑tearing technique that lets subsets of switches be treated independently, thereby reducing memory usage and computational load. An iterative algorithm determines the state of naturally commutated switches, a Gauss‑Jordan unit solves the interface voltages and currents, and custom floating‑point operators provide high accuracy, high‑frequency operation, and low latency. A neutral‑point‑clamped converter case study shows the method’s effectiveness, with simulation results matching a reference model at a 750‑ns time step and 30‑kHz PWM.
The realm of hardware-in-the-loop simulation resorts to field-programmable gate arrays to achieve time steps below 1 $\mu\hbox{s} $. Such low time steps are of importance for the aerospace and automotive industries, where power converters have their switching frequencies in the 10- to 200-kHz range. This paper proposes a network tearing technique that allows subsets of switches to be treated independently, alleviates embedded memory requirements, and reduces the computational burden. An iterative algorithm is used to determine the state of naturally commutated switches, thus offering a realistic model of the power converter, independently of its operation mode or topology. A Gauss-Jordan processing unit is implemented to solve interface voltages/currents from the torn circuit. Custom floating-point operators are used to ensure good accuracy, high-frequency operation, and low computational latency. A neutral-point-clamped converter case study is presented to demonstrate the effectiveness of the method. Simulation results are validated against a reference model at a 750-ns time step and a 30-kHz sine pulsewidth modulation switching frequency.
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