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Error correction circuit using difference-set cyclic code
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2003
Year
Unknown Venue
EngineeringError Control TechniqueVerificationClock SynchronizationFormal VerificationError Correction ReceiverHardware SecurityClock RecoveryError Correction CircuitError CorrectionAsynchronous CircuitsData VerificationComputer EngineeringComputer ScienceError Correction CodeSignal ProcessingFormal MethodsSynchronization CircuitState Machine
Highly reliable operation, short critical path, and small circuit size are key issues. The design uses a state‑machine with a Johnson counter and timer to detect ten bit sequences for synchronization, thereby optimizing circuit size. The receiver, built with a difference‑set cyclic code, achieves a critical path of 4.8, below the average.
An error correction receiver using difference-set cyclic code has been designed. Highly reliable operation, short critical path, and small circuit size are key issues. The synchronization circuit is optimized in its circuit size by detecting 10 kinds of bit sequences for synchronization. The circuit action is governed by state machine combined with a Johnson counter and a timer. The critical path length is estimated to be 4.8, which is less than average value.