IEEE Journal of Solid-State Circuits · 2011 · 38 citations · 21 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsMicrowave EngineeringCmos Circuit DesignHigh-frequency Semiconductor DevicesLow-noise Circuit DesignMicrowave Integrated CircuitsMixed-signal Integrated Circuit DesignRadio-frequency Integrated CircuitsFrequency SynthesisFrequency SynthesizersMillimeter-wave Integrated CircuitsPhase NoiseRadio-frequency Integrated Circuit DesignSige Bicmos Design
We present a 4.4-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> single-chip synthesized signal source with 125 MHz to 32 GHz continuous frequency coverage with a minimum frequency step smaller than 10 Hz. The chip is fabricated in a 0.18-μm SiGe BiCMOS 1P6M technology. A core fractional-N synthesizer using a 20-MHz reference frequency has four LC-VCOs and a 4- to 8-GHz synthesizable range. Post-synthesis blocks extend the frequency coverage up to 32 GHz and down to 125 MHz through frequency multiplication and division. In different operation modes, the chip, including a balanced 50-ohm load driver, consumes from 284 to 498 mW. The phase noise performance achieves -117.6 dBc/Hz at 1-MHz offset from a 6-GHz output frequency and -83 dBc/Hz in-band noise. The integrated phase noise is -28 dBc and the absolute jitter is 1.05 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> at 6-GHz output. The jitter is maintained nearly constant (between 0.9 and 1.2 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> ) across the whole output frequency range.
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