IBM Journal of Research and Development · 1974 · 45 citations · 3 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMemoryDelay ModelingDigital Logic DesignMemory DevicesMemory ModelingMemory Subsystem DesignTiming ModelingMemory CircuitsPropagation Delay ModelingRandom Access Memory (Ram)Random-access MemoryTime-varying Delays
A model of the design process for computer logic is used to estimate the number of bits of memory required to replace a so-called “random logic” circuit. The model can also be used to compare the respective time delays of array logic and random logic.
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