A Scalable 2.4-to-2.7GHz Wi-Fi/WiMAX Discrete-Time Receiver in 65nm CMOS

Abstract

This paper describes a fully integrated scalable discrete-time receiver based on a merged SC mixer, filter and SAR ADC meeting the requirements of IEEE 802.16e and 802.11b/g/n standards. Recent work has shown the use of SC-filtering techniques in radio receivers, where sampling is done early in the RX path. Such discrete-time architectures require an early anti-aliasing (AA) filter prior to sampling. Multiple AA and channel filters with decimation stages have been used to strongly attenuate alias and adjacent channels and to allow sampling of the signal at a reasonable rate at the ADC stage.IF amplifiers are necessary to drive ADC input stage. The direct-conversion receiver architecture proposed here is based on a fully-passive CMOS approach. It is composed of one transconductance LNA and a resistive attenuator.