Low-voltage-driven top-gate ZnO thin-film transistors with polymer/high-k oxide double-layer dielectric

Abstract

The authors report on the fabrication of a low-voltage-driven top-gate ZnO thin-film transistor with a polymer/high-k oxide double-layer dielectric. Hybrid double-layer dielectric (k=∼9.8) was formed on patterned ZnO through sequential deposition processes: spin casting of 45-nm-thin poly-4-vinylphenol and e-beam evaporation of 50-nm-thick amorphous high-k oxide (CeO2–SiO2 mixture). Room-temperature-deposited ZnO channel exhibits much rougher surfaces compared to that of 100°C deposited ZnO, so that enhanced device performances were achieved from a ZnO thin-film transistor (TFT) prepared with 100°C deposited ZnO: ∼0.48cm2∕Vs for field-effect mobility and ∼5×103 for on/off current ratio. Adopting our top-gate ZnO-TFT, a load-resistance inverter was set up and demonstrated decent static and dynamic operations at 3V.