Extended abstract: The butterfly PUF protecting IP on every FPGA

TLDR

IP protection for FPGA designs relies mainly on bitstream encryption, but alternative physical unclonable function (PUF) approaches have been proposed, with early FPGA PUFs based on SRAM startup values limited to devices that support uninitialized SRAM. This work proposes a butterfly PUF that can be implemented on all FPGA families to provide IP protection. The butterfly PUF is a new structure that generates volatile secret keys from the FPGA’s physical characteristics, enabling secure identification and key generation. Experimental results demonstrate the butterfly PUF’s effective identification and key generation capabilities.

Abstract

IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream encryption. An alternative solution was advocated in (E. Simpson and P. Schaumont, 2006). Simpson and Schaumont proposed a new approach based on physical unclonable functions (PUFs) for IP protection on FPGAs. PUFs are a unique class of physical systems that extract secrets from complex physical characteristics of the integrated circuits which along with the properties of unclonability provide a highly secure means of generating volatile secret keys for cryptographic operations. However, the first practical PUF on an FPGA was proposed only later in (J. Guajardo et al., 2007) based on the startup values of embedded SRAM memories which are intrinsic in some of the current FPGAs. The disadvantage of these intrinsic SRAM PUFs is that not all FPGAs support uninitialized SRAM memory. In this paper, we propose a new PUF structure called the butterfly PUF that can be used on all types of FPGAs. We also present experimental results showing their identification and key generation capabilities.