A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC

Abstract

This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma modulators, it does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a low-jitter clock. Therefore, it uses less area than comparable conventional delta-sigma modulators, and the architecture is well-suited to IC processes optimized for fast digital circuitry. The prototype IC is implemented in 65 nm LP CMOS technology with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8-17 mW, 0.5-1.15 GHz, 3.9-18 MHz, and 67-78 dB, respectively, and an active area of 0.07.