An efficient FPGA implementation of the OS-CFAR processor

Abstract

A new structure for an efficient Field Programmable Gate Array, FPGA, implementation of the order statistics CFAR detector, based on the (N-K+1)-th maximum determination, is proposed. By showing that the determination of the K-th order out of N reference cells is equivalent to selecting the (N + 1 - K)-th maximum, the detector that uses N reference cells can be implemented using only (N-1) comparators and (N-1) inverters. The proposed architecture shows that it can be implemented with the advantages of a parallel structure and allows an important optimization of the required FPGA hardware resources utilization. The structure has been implemented using a Virtex-II XC2V1000-4FG456C FPGA board. The FPGA implementation results are presented and discussed.