A 300 MHz 115 W 32 b bipolar ECL microprocessor with on-chip caches

Abstract

A full-custom 32-b ECL (emitter coupled logic) microprocessor which uses a 1.0- mu m-drawn single-poly technology with four layers of aluminum and one layer of gold interconnect is described. The 15.4-mm*12.6-mm die contains 468-k bipolar transistors (f/sub t/=13 GHz) and 206-k resistors. The chip implements a subset of an existing RISC (reduced instruction set computer) architecture. The machine has five pipeline stages, each one clock cycle long. A 128-b bus is used for incoming data; a 64-b bus is used for outgoing data. The chip uses a single-phase differential clock. The clock distribution network consists of three levels of H-trees. The 2-kB instruction and data caches use a 16-B line, contain byte parity, and are direct-mapped. The chip contains 30 internal master bias circuits, whose outputs are wire-ORed together. The logic portions of the chip primarily use a single-ended 575-mV swing.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>