InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR

Abstract

A prototype 13-b 1.33-Gsps digital-to-analog converter (DAC) implemented in a unique heterogeneous integration process (combining 0.45-μm InP HBT with 0.18-μm CMOS) is presented. Measured performance of greater than 70 dB SFDR is achieved across a 500-MHz bandwidth centered at 1 GHz (second Nyquist band). Heterogeneous integration enables each circuit element to be implemented in the transistor technology best suited to the circuit function. Low dc power is achieved by implementing the digital front-end in a standard silicon CMOS technology, while InP HBT technology is used to implement the high-speed/high-precision current-steering DAC core. The core DAC employs a segmented architecture with three unary most significant bits and an R-2R ladder for the ten least significant bits. No calibration circuitry is required to achieve better than 11 b of dc linearity. Dynamic performance is enhanced by employing an ultra-high-linearity return-to-zero (RZ) analog output deglitcher switch. Measured performance data for three different circuit design variations of the output switch (incorporating a varying mix of CMOS and InP HBT devices) is presented.