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Oxidation of silicon nanowires for top-gated field effect transistors
32
Citations
32
References
2008
Year
SemiconductorsSemiconductor TechnologyElectrical EngineeringElectronic DevicesSilicon NanowiresElectronic MaterialsEngineeringSemiconductor DeviceNanoelectronicsNanotechnologyApplied PhysicsSmallest NanowiresSemiconductor Device FabricationP-type Silicon NanowiresMicroelectronicsDry Thermal OxidationSemiconductor Nanostructures
The oxidation of unintentionally doped p-type silicon nanowires grown by the vapor-liquid-solid (VLS) method and their integration into top-gated field effect transistors is reported. Dry thermal oxidation of as-grown silicon nanowires with diameters ranging from 20to400nm was carried out at 700 and 900°C with or without the addition of a chlorinated gas source. The oxidation rate was strongly dependent on the as-grown nanowire diameter, with the large-diameter nanowires oxidizing up to five times faster than the smallest nanowires at 900°C. At each diameter, the addition of trichloroethane (TCA) enhanced the rate compared to oxidation in pure O2. Top-gated field effect transistors fabricated from nanowires oxidized at 700°C had significantly less hysteresis in their subthreshold properties when TCA was added, but oxidation at 900°C with or without TCA provided hysteresis-free devices with improved subthreshold slope. Such enhancements in the electrical properties are expected based on advances in planar silicon process technology and emphasizes the importance of incorporating these techniques for VLS-grown nanowire devices.
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