A 20 Gb/s 1:4 DEMUX with Near-Rail-to-Rail Logic Swing in 90 nm CMOS process

Abstract

A 9.5 mW 20 Gb/s 40times70 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> inductorless 1:4 DEMUX in 90 nm CMOS process is presented. In order to reduce power and area, the DEMUX uses a multi-phase clock architecture that requires a smaller number of latches operating at a slower clock rate than in the conventional tree architecture. To provide low-voltage scalability, the latches operate with a near-tail-to-rail logic swing. It is realized without significant speed penalty by adopting current-sourceless CML-type latches with unconventional settings. It offers a larger noise margin and elimination of logic level converters too. The well-balanced scalable design could possibly broaden the applications of high-speed SerDes in the coming ultralow-voltage many-core era.