A 675 Mbps, 4 $\times$ 4 64-QAM K-Best MIMO Detector in 0.13 $\mu{\rm m}$ CMOS

Abstract

This paper introduces a novel scalable pipelined VLSI architecture for a 4 × 4 64-QAM hard-output multiple-input-multiple-output (MIMO) detector based on K-best lattice decoders. The key contribution is a means of expanding the intermediate nodes of the search tree on-demand, rather than exhaustively, along with three types of distributed sorters operating in a pipelined structure. The proposed architecture has a fixed critical path independent of the constellation size, on-demand expansion scheme, efficient distributed sorters, and is scalable to higher number of antennas. Fabricated in 0.13 μm CMOS, it occupies 0.95 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area. Operating at 282 MHz clock frequency, it dissipates 135 mW at 1.3 V supply with no BER performance loss. It achieves an SNR-independent throughput of 675 Mbps satisfying the requirements of IEEE 802.16m and long term evolution (LTE) systems. The measurements confirm that this design consumes 3.0 × less energy/bit and operates at a significantly higher throughput compared to the best previously published design.