Publication | Closed Access
A heuristic procedure for ordering MOS arrays
25
Citations
3
References
1975
Year
Physical Design (Electronics)Array ComputingEngineeringVlsi DesignCircuit DesignElectronic Design AutomationSimulated AnnealingSorting AlgorithmChip AreaComputer EngineeringComputer ArchitectureHeuristic ProcedureComputational ComplexityComputer ScienceOptimal OrderingCombinatorial OptimizationMicroelectronics
For automated layout of one-dimensional MOS gates arrays, a heuristic procedure, determining the optimal ordering of gates to minimize the chip area, is presented.
| Year | Citations | |
|---|---|---|
Page 1
Page 1