Optimization principles and application performance evaluation of a multithreaded GPU using CUDA

TLDR

GPUs are increasingly used as commodity data‑parallel coprocessors, and recent generations offer easier programmability, greater generality, and maintain high memory bandwidth and computational power. This work aims to shift GPGPU research from ad hoc porting toward establishing principles and strategies for efficiently mapping computations onto graphics hardware, illustrated through the GeForce 8800 GTX. Performance on the GeForce 8800 GTX hinges on massive multithreading that balances per‑thread resource use—registers, on‑chip memory, threads per multiprocessor, and global memory bandwidth—while reordering off‑chip memory accesses and applying classical optimizations to reduce operations. Applying these strategies to diverse applications yields kernel speedups of 10.5×–457× and overall application speedups of 1.16×–431×.

Abstract

GPUs have recently attracted the attention of many application developers as commodity data-parallel coprocessors. The newest generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. This opportunity should redirect efforts in GPGPU research from ad hoc porting of applications to establishing principles and strategies that allow efficient mapping of computation to graphics hardware. In this work we discuss the GeForce 8800 GTX processor's organization, features, and generalized optimization strategies. Key to performance on this platform is using massive multithreading to utilize the large number of cores and hide global memory latency. To achieve this, developers face the challenge of striking the right balance between each thread's resource usage and the number of simultaneously active threads. The resources to manage include the number of registers and the amount of on-chip memory used per thread, number of threads per multiprocessor, and global memory bandwidth. We also obtain increased performance by reordering accesses to off-chip memory to combine requests to the same or contiguous memory locations and apply classical optimizations to reduce the number of executed operations. We apply these strategies across a variety of applications and domains and achieve between a 10.5X to 457X speedup in kernel codes and between 1.16X to 431X total application speedup.