Settling Time Optimization for Three-Stage CMOS Amplifier Topologies

Abstract

A new settling-time-oriented design methodology for the most common three-stage operational amplifier (op-amp) schemes reported in the literature is presented in this paper. The proposed approach allows the systematic sizing of the compensation network in order to reach the best closed-loop op-amp settling behavior. To demonstrate the effectiveness of the methodology and the correctness of the analysis, the examined three-stage op-amp topologies are designed in a commercial 0.35-¿m CMOS technology. Circuit simulations show that the proposed design approach, for each investigated topology, guarantees a significant settling time reduction with respect to the compensation network sizing strategies proposed in the past. An ad-hoc figure of merit, which evaluates the trade-off between the settling time, the load capacitance and the total op-amp stage transconductances, is also defined in order to estimate the op-amp efficiency in terms of time-domain performances.