A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS

Abstract

This paper details a duplex architecture coupled with a linear Class-AB push-pull output stage that maximizes the power efficiency of linear wideband drivers for high-speed transceivers. The duplex driver merges transmission, reception, and termination; eliminates hybrid and termination overhead; and enables adaptive echo cancellation and rail-to-rail full-duplex operation. Implemented in 28 nm CMOS, this GPHY driver passes the 1000BASE-T and 100BASE-TX compliance tests using a 2.5 V supply and meets the transmit specifications for the half-duplex 10BASE-T Ethernet using a 3.3 V supply.