Realization of a Silicon Nanowire Vertical Surround‐Gate Field‐Effect Transistor

Abstract

A generic process for fabricating vertical surround-gate field-effect transistors (FETs) from epitaxially grown silicon nanowires is presented. The process is demonstrated using n-type Si nanowires grown on a p-type substrate in ultrahigh vacuum using a Au catalyst. The process consists of various deposition and etching steps; no chemical or mechanical polishing is required. Individual as well as arrays of vertical surround-gate FETs can be fabricated.