2-Bit magnitude comparator using GDI technique

Abstract

In recent years, low power design has become one of the prime focuses for the digital VLSI circuit. Keeping the same in mind a new design of 2-Bit GDI based Magnitude Comparator has been proposed and implemented with the help of full adder which is the basic building block of ALU. Proposed GDI technique based magnitude comparator has an advantage of less power consumption with respect to various design parameters; less on-chip area covered as less number of transistors are required in circuit design as compared to conventional CMOS magnitude comparator. Both the circuits are designed and simulated using Tanner EDA Tool version 12.6 at 45nm process technology.