Some schemes of realization digital FIR filters on FPGA for communication applications

Abstract

Realization of digital Finite-Impulse-Response (FIR) filters are so important issues for digital communications and signal processing applications which is the main contribution of this paper. The direct and transposed architectures are employed to implement FIR filters on field-programmable-gate-array (FPGA) using a single SPARTAN 2 chip, XC2S50-5I-tq144, from Xilinx, Inc. The Verilog hardware description language is used for designing different schemes of FIR filter. The effects of coefficient symmetry and implementing multiplier blocks by shift and add operators on frequency and FPGA chip area occupation metrics are studied. Simulation results demonstrate improving FPGA-based solutions for digital FIR filter design.