Parametric DFM Solution for Analog Circuits: Electrical-Driven Hotspot Detection, Analysis, and Correction Flow

Abstract

As VLSI technology pushes into advanced nodes, designers and foundries have exposed a hitherto insignificant set of yield problems. To combat yield failures, the semiconductor industry has deployed new tools and methodologies commonly referred to as design for manufacturing (DFM). Most of the early DFM efforts concentrated on catastrophic failures, or physical DFM problems. Recently, there has been an increased emphasis on parametric yield issues, referred to as electrical-DFM (e-DFM). In this paper, we present a complete e-DFM solution that detects, analyzes, and fixes electrical hotspots (e-hotspots) within an analog circuit design that are caused by different process variations. Novel algorithms are proposed to implement the engines used to develop this solution. The solution is examined on a 130-nm parametrically-failing level shifter circuit, and verified with silicon wafer measurements that confirm the existence of parametric yield issues in the design. Additional experiments are applied on a 65-nm industrial operational amplifier and voltage control oscillator (VCO). E-hotspot devices with a 27.7% variation in dc current are identified. After fixing the e-hotspots, the dc current variation in these devices is dramatically reduced to 7%, which meets the designer acceptance criteria, while saving the original VCO specifications.