60 GHz injection locked frequency quadrupler with quadrature outputs in 65 nm CMOS process

Abstract

This paper presents a LC-based sub-harmonic injection-locked frequency quadrupler which multiplies a 15 GHz input to 60 GHz quadrature(I/Q) output signals. The proposed quadrupler can use a lower-frequency PLL for incident signal than doublers and triplers, which is very advantageous to implement a wide-tuning and low-phase-noise PLL. The proposed frequency quadrupler is implemented by using a 65 nm CMOS process. It consumes 5.9 mW with a 0.6 V supply voltage, and the core layout area is 160 ¿m × 110 ¿m.