Modular dynamic reconfiguration in Virtex FPGAs

TLDR

Modular FPGA systems can load and unload modules at run time, but Virtex and Spartan devices’ configuration architecture hinders true modular reconfiguration, confining research to theoretical or constrained models. The study compares two methods for achieving modular reconfiguration on Virtex FPGAs. The first method trades simplicity and speed for limited geometry and connectivity, while the second method, recently developed, permits arbitrary module placement, bridging theory and practice. The newer method incurs longer reconfiguration times but has been successfully applied in three projects, including the first modular reconfiguration implementation on a Virtex‑4.

Abstract

Modular systems implemented on field-programmable gate arrays (FPGAs) can benefit from being able to load and unload modules at run-time, a concept that is of much interest in the research community. Although dynamic partial reconfiguration is possible in Virtex and Spartan series FPGAs, the configuration architecture of these devices is not amenable to modular reconfiguration, a limitation which has relegated research to theoretical or compromised resource allocation models. Two methods for implementing modular reconfiguration in Virtex FPGAs are compared and contrasted. The first method offers simplicity and fast reconfiguration times, but limits the geometry and connectivity of the system. The second method, developed recently, enables modules to be allocated arbitrary areas of the FPGA, bridging the gap between theory and reality and unlocking the latent potential of dynamic reconfiguration. The cost of this advancement is increased reconfiguration time. The second method has been demonstrated in three applications, including the first reported implementation of modular reconfiguration in a Virtex-4 device.