A 14b 100MS/s Pipelined ADC with a Merged Active S/H and First MDAC

Abstract

The prototype ADC is implemented in 0.18mum dual gate-oxide (DGO) CMOS technology and achieves 72.4dB SNR and 88.5dB SFDR at 100MS/s with a 46MHz input while consuming 230mW from a 3V supply. Recently, power saving has been achieved by removing the explicit active S/H. Instead of removing the S/H, this work solves these drawbacks by merging the active S/H amplifier with the first MDAC (SMDAC). Thus, the ADC achieves low-power operation without sacrificing speed or accuracy.