1c:I[419806,["/_next/static/chunks/bb923814e1f4d2e9.js","/_next/static/chunks/dd3ee9f5b7716ca6.js","/_next/static/chunks/4204a0ae82542ca8.js","/_next/static/chunks/30036bedc5269936.js","/_next/static/chunks/6e1aa89a642f40be.js","/_next/static/chunks/cd5e572bc3e4eb92.js","/_next/static/chunks/8ffd0b71567920d8.js","/_next/static/chunks/67ea6dfd21f16c5f.js","/_next/static/chunks/24eb4379f68013fd.js","/_next/static/chunks/b8cd775ffdf935bd.js","/_next/static/chunks/983103cd9eb7b428.js","/_next/static/chunks/d4ac9dcf27f6ff52.js","/_next/static/chunks/294b9525248c8e5f.js"],"default"] 1d:T514,In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency g _m /I _d , intrinsic gain g _m /g _d , cutoff frequency f _t , and maximum oscillation frequency f _max . The results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog/RF applications. The impact of nanowire cross-sectional shape fluctuation that is caused by process variation is studied and found to be relatively severe, and the acceptable variation tolerance for RF integrated circuit design is given1e:T42e,The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance. In this paper, we have investigated the effects of gate misalignment in the DMDG SOI n-MOSFET. In this regard, analytical modeling and extensive simulations have been carried out to analyze the gate misalignment effects on device performance like surface potential, electric field, threshold voltage, subthreshold slope, drain-induced barrier lowering, drain current, and transconductance. Considering the fact that gate misalignment can occur on any side of the gate, both source- and drain-side misalignments have been discussed. Analytical and simulated results are found to be in good agreement, which authenticate our proposed model for the DMDG structure.

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