New Twin Crossbar Architecture of Binary Memristors for Low-Power Image Recognition With Discrete Cosine Transform

Abstract

In this paper, we propose a new twin crossbar architecture of binary memristors for low-power image recognition. In the new twin crossbar, we use two identical memristor arrays instead of using the previous complementary memristor arrays of M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> . Thereby, we can apply the discrete cosine transform (DCT) algorithm to reduce the number of low-resistance state (LRS) cells in the two identical M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> arrays. With the reduced number of LRS cells in two M <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> arrays, the power consumption in the crossbar can be significantly saved compared to the previous complementary crossbar that is not suitable to DCT. When the number of discarded coefficients in the DCT matrix is 56.25%, 67.19%, 76.56%, and 84.38%, the power consumption of the new twin crossbar is reduced by 51.7%, 61.3%, 69.9%, and 77.4%, respectively, compared to the previous complementary one.