A 1.8-mW CMOS /spl Sigma//spl Delta/ modulator with integrated mixer for A/D conversion of IF signals

Abstract

In this paper, the design of a continuous-time baseband sigma-delta (/spl Sigma//spl Delta/) modulator with an integrated mixer for intermediate-frequency (IF) analog-to-digital conversion is presented. This highly linear IF /spl Sigma//spl Delta/ modulator digitizes a GSM channel at intermediate frequencies up to 50 MHz. The sampling rate is not related to the input IF and is 13.0 MHz in this design. Power consumption is 1.8 mW from a 2.5-V supply. Measured dynamic range is 82 dB, and third-order intermodulation distortion is -84 dB for two -6-dBV IF input tones. Two modulators in quadrature configuration provide 200-kHz GSM bandwidth. Active area of a single IF /spl Sigma//spl Delta/ modulator is 0.2 mm/sup 2/ in 0.35-/spl mu/m CMOS.