A New Method of Producing Laterally Stable PDC Drill Bits

Abstract

Abstract Bit Whirl is well documented as a major cause of damage to PDC drill bits, resulting in short runs, low ROP, high cost per foot, poor hole quality and downhole tool damage. Hence, consistent lateral stability is highly desirable in PDC bits. The paper presents a new method of producing PDC drill bits that reduce or eliminate bit whirl. Traditionally, attempts to design laterally stable PDC bits have assumed that the forces generated by the bit during stable drilling cause it to begin whirling. The new approach assumes that it is the response of the bit to forced motion off its centre that causes whirl. The new approach has been validated theoretically, in the lab and the field. Test results from a full-scale drilling rig indicate that this method is superior to existing methods at minimizing bit whirl. This new method was successfully validated through an extensive field test program undertaken in Northwest USA, involving high-speed downhole measurements from both conventional 7 7/8″ diameter PDC drill bits and bits designed using this new method. These results demonstrated that the conventional PDC drill bits exhibited bit whirl throughout the run. The bits designed using the new method completely eliminated bit whirl. The performance benefits of this new method were demonstrated in a 16″ section in the Middle East, where lateral vibrations are a significant problem. Prior to testing the new method PDC bit, bit optimization led to the use of high imbalance force designs to minimize lateral vibration. The first test of the new method laterally stable PDC bit set field records for ROP, footage and cost per foot compared to over 50 runs of these "Anti-Whirl"1 designs, resulting in savings of over $50,000 per run. This paper demonstrates how the use of this new method can eliminate whirl in both laboratory and field environments, and deliver significant performance improvements over existing stability techniques. This new method represents a major step forward in the design of PDC bits to mitigate bit whirl, and has been proven to reduce bit damage, increase run lengths, increase ROP and deliver sizeable savings for operators.