PLEST: A Program for Area Estimation of VLSI Integrated Circuits

Abstract

This paper describes PLEST, a program for estimating the area of standard cell layouts as part of the more general ARREST area estimator embedded in the ADAM system. PLEST is based on a probabilistic model for placement of logic. Given various design parameters, PLEST generates a range of estimates for the possible shapes of the block layout. The program was applied to a set of six layouts. The estimated chip area is, for all six chips, within 10% of the measured area. Further research will be aimed at estimating layout area consumption starting from the register-transfer level design description.