Random Variation Analysis and Variation-Aware Design of Symmetric Tunnel Field-Effect Transistor

Abstract

A variation-immune symmetric tunnel field-effect transistor (S-TFET) is proposed for the first time to implement bidirectional current flows (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 3.6 μA/μm, IOFF = 23 pA/μm at VDD = 0.5 V) with the steep-switching feature of a subthreshold slope (SS) <; 60 mV/dec (SS = 47 mV/dec) and to alleviate the impact of random variation. A random variation analysis with the three major random variation sources, i.e., line-edge roughness, random dopant fluctuation, and work-function variation, is performed to quantitatively evaluate the impact of each variation source on the performance of the device. To perform variation-aware design for the S-TFET, the key device parameter (i.e., the thickness of the intrinsically doped silicon pad layer) is optimized to minimize the impact of random variation on the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and SS. For ultralow power applications with a sub-0.5 V power supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ), the variation-robust S-TFET is one of several promising device structures.