2006 · 83 citations · 3 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMicroelectronicsLeakage Power ReductionLow-power Cache DesignMemory Subsystem DesignMulticore Processor DesignPower ManagementProcessor Core DesignCache DesignCache Hierarchy DesignCache Leakage ReductionEnergy-efficient Multicore DesignLeakage Current ReductionLeakage-aware Cache DesignLow-power Data Cache DesignPower-performance-area Tradeoffs
A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes
3
SRAM design on 65nm CMOS technology with integrated leakage reduction scheme
Kedong Zhang, Uma Bhattacharya, Z. Chen et al. · 2004 · 75 citations
Engineering, Computer Engineering, Electrical Engineering +17