A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache

Abstract

A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes