Publication | Closed Access
Single-Event Soft Errors in CMOS Logic
24
Citations
7
References
2012
Year
EngineeringVlsi DesignError Control TechniqueVerificationComputer ArchitectureSe Clock JitterFormal VerificationInterconnect (Integrated Circuits)Electromagnetic CompatibilityHardware SecurityReliability EngineeringAdvanced Packaging (Semiconductors)Electronic PackagingSe Crosstalk NoiseFailure DetectionElectrical EngineeringComputer EngineeringHspice SimulationsCmos LogicMicroelectronicsVlsi ArchitectureFormal MethodsBeyond CmosFault Injection
In this article, various mechanisms for combinational logic-related radiation induced soft errors such as SE-induced soft delays, SE clock jitter and clock pulse, and SE crosstalk effects have been discussed. Our analysis shows that increasing SE crosstalk noise and delay effects occur with smaller technologies. This work has finally discussed hardening techniques for SE crosstalk noise and delay. Results are shown using HSpice Simulations with interconnect and device parameters derived from Predictive Technology Model for 65 nm.
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