SINIS fabrication process for realizing integrated circuits in RSFQ impulse logic

Abstract

At PTB, a new type of fabrication process has been developed to verify rapid single flux quantum (RSFQ) integrated circuits based on intrinsically shunted two-tunnel Josephson junctions (JJs). The process has been realized in LTS implementation using SINIS technology. A variety of single JJs, junction arrays and test circuits have been fabricated and experimentally investigated. The critical current densities of the junctions were set to a nominal value of jC = 500 A cm-2, with values of the characteristic voltage VC equal to or larger than 160 µV. The JJs show nearly hysteresis-free behaviour (less than 10%); the intrawafer parameter spread is smaller than ±10%. Various basic RSFQ circuits have been realized with operation margins of bias currents of larger than ±20%.